Memory speed and memory capacity continue to increase to meet the demands of system applications. Some of these system applications include mobile electronic systems that have limited space and limited power resources. In mobile applications, such as cellular telephones and personal digital assistants (PDAs), memory cell density and power consumption are issues for future generations.
To address these issues, the industry is developing random access memories (RAMs) for mobile applications. One type of RAM, referred to as CellularRAM, is a high performance and low power memory designed to meet the growing memory density and bandwidth demands of future designs. CellularRAM is a pseudo static RAM (PSRAM) that offers a lower cost per bit ratio than typical solutions. Also, CellularRAM offers static random access memory (SRAM) pin and function compatibility, external refresh-free operation, and a low power design. CellularRAM devices are drop-in replacements for most asynchronous low power SRAMs currently used in mobile applications, such as cellular telephones.
Each memory cell in a DRAM includes a transistor and a capacitor. The capacitor is charged and discharged to represent a logic “0” or a logic “1”. During a read operation, a data bit value stored on the capacitor is read. During a write operation, a data bit value is written to the capacitor. A read operation on a memory cell is destructive. After each read operation, the capacitor is recharged or discharged to the data value that was just read. In addition, even without read operations, the charge on the capacitor discharges over time.
To retain a stored data bit value, the memory cell is refreshed periodically by reading and/or writing to the memory cell. All memory cells within a DRAM are periodically refreshed to maintain their values. During self-refresh, the rate at which the memory cells are refreshed is typically defined by a self-refresh module including a self-refresh oscillator and trimming circuits. The self-refresh oscillator and trimming circuits typically provide a self-refresh pulse for initiating a self-refresh of the memory cells. The base frequency of the self-refresh oscillator contributes to standby power consumption. Therefore, by reducing the oscillator base frequency of the self-refresh oscillator, the standby power consumption can be reduced.